FIG. 1 depicts a circuit diagram of a portion of an electrostatic discharge (ESD) protection circuit 10 that contains an Input/Output (I/O) pad 20. The I/O pad 20 further contains bondpad 24, diodes 25 and 26, and MOSFETS 27 and 28. Within this specification the first current electrode of MOSFET devices is called the source terminal, which is coupled to one of the power supply terminals VDD or VSS unless otherwise specified. The second current electrode of those same MOSFET devices is called the drain terminal. The drain terminal of MOSFET 28 is coupled to bondpad 24, as is the drain terminal of MOSFET 27. In I/O pad 20, the anode of diode 26 is coupled to bondpad 24 and the cathode of diode 26 is coupled to supply terminal VDD. Similarly, the cathode of diode 25 is coupled to the bondpad 24 and the anode of diode 25 coupled to terminal VSS. The ESD protection circuit 10 further contains a rail clamp 30 with a first current electrode coupled to supply terminal VDD and a second current electrode coupled supply terminal VSS. ESD protection circuit 10 also contains a diode 40 where the anode of diode 40 is coupled to supply rail VSS and the cathode of diode 40 is coupled to supply terminal VDD. The ESD protection circuit 10 also contains parasitic bus resistances RP and RG in the supply lines. These are not explicit resistor elements, but rather ones that exist by default due to the inherent resistance of any electrical conductor. In general, the greater the distance between the I/O pad 20 and the ESD rail clamp 30 and bus diode 40, the greater the value of the parasitic resistances RP and RG.
Integrated circuits must be protected against electrostatic discharges in order to prevent permanent damage that can impair or eliminate desired functionality. ESD damage normally occurs in the MOSFET devices or interconnecting layers used to couple MOSFETs together to form a circuit. Each pin in an integrated circuit must be coupled to an appropriate ESD protection circuit such that the ESD discharge current is shunted away from the internal portions of the chip that are the most sensitive to damage. As such, ESD discharge paths must be provided between every pair of pins in an IC for both positive and negative polarities.
The function of diode 26 in FIG. 1 is to provide a shunting path to the rail VDD for ESD currents produced by ESD potentials applied to bondpad 24 which are significantly more positive than anywhere else on the IC. Similarly, the function of diode 25 is to provide a shunting path for ESD currents that are produced by ESD potentials that are significantly more negative than elsewhere on the IC. The function of rail clamp 30 is to provide a coupling between the rails VDD and VSS for those ESD paths that require such a coupling in order to complete the discharge loop. For example, for pad positive-to-VSS stress, where bondpad 24 is taken positive with respect to the rail VSS, the ESD discharge current 100 flows from bondpad 24, through diode 26, along the rail VDD (through the parasitic resistor RP) and back to the rail VSS through rail clamp 30. In general, the goal is to keep the maximum voltage built-up in the discharge loop to within acceptable limits. Similarly, for pad positive-to-VDD, where the bondpad 24 is taken positive relative to the rail VDD, discharge current 102 flows from bondpad 24, through diode 26 and to the rail VDD where the circuit is completed.
For negative ESD events applied to bondpad 24 such as pad negative-to-VSS stress, ESD current 101 flows from the rail VSS (which is now positive relative to the bondpad 24) through diode 25 and back to bondpad 24 where the circuit is completed. Finally, for pad negative-to-VDD, the ESD current 103 flows from the rail VDD, through rail clamp 30, along the rail VSS (through parasitic resistance RG) and back to bondpad 24 through diode 25. Again, the goal is to keep the maximum voltage built-up in the discharge loop to within acceptable limits. In each case described so far, diode 25 or 26 alone or a combination of diode 25 or 26 and rail clamp 30, act to provide a shunting path for the ESD current such that these currents are kept from the sensitive internal portions of the chip. For ESD stress applied to bondpad 24, output buffer transistors 27 and 28 are the most susceptible to damage and so is any other input buffer circuitry (not shown) coupled to bondpad 24.
Just as ESD pulses can be applied between the I/O pads and the supply rails, ESD discharges can occur between the power supply rails. For example for rail VDD positive-to-VSS stress, ESD current 104 flows through the rail clamp 30 from the rail VDD to the rail VSS. For rail VSS positive-to-VDD stress, ESD current 105 flows from the rail VSS, through diode 40 and to the rail VDD. Thus, the rail clamp circuit is a fundamental component in providing a discharge path for ESD polarities (positive or negative) which cause the first current electrode of the rail clamp to be more positive than its second current electrode. Although the several ESD discharge paths shown in FIG. 1, there are other paths not shown between other pairs of pins which are well known to one skilled in the art. These have not been described here simply for brevity and do not detract in any way from the description or understanding of the invention described herein.
ESD discharges are brief transient events that are usually less than one microsecond in duration. Furthermore, the rise times associated with these brief pulses are usually less than roughly twenty nanoseconds. When ESD pulses are applied to the I/O pads of a chip, they produce similar brief, fast rise time potentials on the power supply rails due to the presence of ESD protection diodes 25 and 26 in FIG. 1. Thus, the rail clamp circuit must be able to detect these fast transients and begin conducting so as to shunt the resulting ESD current. However, the rail clamp must not respond to the much slower rise times (greater than 1 millisecond) which are present on the power supply rails during normal power-up events in regular chip operation. If the ESD rail clamp were to trigger and conduct during normal power-up events, the desired operation of the IC could be compromised. Furthermore, in addition to triggering when needed for ESD protection, the rail clamp circuits must stay in a highly conductive state for the entire duration of the ESD pulse so that all of the ESD energy is safely discharged. If the rail clamp circuit were to shut-off prematurely, damaging potentials would build-up quickly between the power rails and cause device failure.
FIG. 2 depicts a wider portion of an integrated circuit that shows how rail clamp 30 can be placed relative to the I/O pads it is protecting. Here, rail clamp 30 has been placed in the VSS pads in the chip that are responsible for supplying power connections for the IC. The rail clamp 30 can also be placed in VDD pads. These placements are shown as 30L1 and 30R1. In this manner, many I/O cells (20L2, 20L1, 20, 20R1, 20R2) are able to share ESD rail clamp 30L1 and 30R1 that results in more robust ESD protection and reduced chip area. Alternatively, the size of an individual rail clamp can be reduced if more than one can be relied upon to conduct ESD current that also saves die area. In general, the sum total of parasitic power and ground rail resistances (RPL2, RPL1 RP RPR1, RPR2) and (RGL2, RGL1 RG RGR1, RGR2) around the ESD discharge loop sets the limit on how far apart ESD rail clamps can be spaced in order to achieve a given level of ESD protection. The overall goal is to keep the maximum voltage that occurs at the bondpad during an ESD discharge within acceptable limits so that damage does not occur in the sensitive circuit elements.
In an effort to mitigate the effects of parasitic bus resistance, one may distribute the ESD rail clamps locally in the I/O cells themselves (20BL1, 20B, 20BR1). This is shown in FIG. 3 where several smaller local clamps are used where one is placed in each I/O pad. In this manner, several ESD rail clamps must now participate in the ESD event to achieve robust protection but the effects of power and ground rail resistances may be reduced over locating the larger clamps in more centralized locations. In general one skilled in the art is able to make a determination as to whether the scheme described in FIG. 3 or in FIG. 2 is more applicable to their particular application. This in no way limits the general usage of the ESD rail clamp described herein, as one skilled in the art is able to easily scale the relative sizes of the clamp so that an optimal tradeoff is achieved.